硬件问题
最初に、各 SoC のハードウェア設計ガイドラインを参照することをお勧めします。ご不明な点がございましたら、以下のフォームにご記入ください。
| Examination of Customer Schematics | ||
|---|---|---|
| Types | Examination Items | Results |
| Power Supply and Ground | 1. The external power supply voltage and supply current meet the demand (500 mA and above). The power efficiency has been taken into consideration. | Loading... |
| 2. There is ESD protection for the power input port. | Loading... | |
| 3. All the power pins of the chip are connected to the power supply as required and the appropriate decoupling capacitors are placed as required. An LC filter circuit is added to the PA power supply to suppress high-frequency harmonics. The value of LC should be confirmed with further tests. | Loading... | |
| 4. There is a divide between analog power and digital power, as well as between analog ground and digital ground. | Loading... | |
| 5. The only ground pin of Espressif's chips is at the bottom of the chip. Check if the pin is connected to the ground when drawing the schematics. | Loading... | |
| 6. When using Espressif's modules, it is recommended that the Ground PAD at the bottom of the module be connected to the ground for better heat dissipation. | Loading... | |
| 7. Others | Loading... | |
| RF | 1. There is a reserved π-matching network (CLC structure recommended) for impedance matching of the external antennas. | Loading... |
| 2. If there are both built-in and external antennas in the design, check if a compatible circuit or antenna switch selection circuit is added. | Loading... | |
| 3. Check whether RF test points are added at appropriate positions. (It is recommended that users add them after the first π-matching circuit). | Loading... | |
| 4. Others | Loading... | |
| Clock | 1. If the part numbers of crystals are provided, check whether the tolerance, load capacitance, power supply voltage, output form of the passive crystal or active crystal meet the requirements. | Loading... |
| 2. When using ESP32, it is recommended that users reserve a 0R/50R series resistor on the XTAL_P line. | Loading... | |
| 3. Others | Loading... | |
| Reset / Enable | 1. CHIP_EN/CHIP_PU needs to be booted on later than the power supply pin, and an external RC delay circuit (R = 10K, C = 0.1 μF) should be added. | Loading... |
| 2. CHIP_EN/CHIP_PU is active high and cannot be left floating. | Loading... | |
| 3. It is recommended that users use CHIP_EN/CHIP_PU to reset the ESP8266EX or ESP32. | Loading... | |
| 4. Others | Loading... | |
| Sleep / Wakeup | 1. When ESP8266EX is put into Deep-sleep, connect XPD_DCDC/GPIO16 or an external GPIO to EXT_RSTB to wake up the chip. | Loading... |
| 2. To use the wake-up function of ESP8689, use one of the GPIO ports to wake up the host. | Loading... | |
| 3. Others | Loading... | |
| External Resistance | 1. Ensure that the value and tolerance of external resistor and capacitor are in accordance with the reference design provided by Espressif. | Loading... |
| 2. Others | Loading... | |
| IO Application | 1. Check if the power-up status of Strapping ioses meet the requirements for the mode to be entered. | Loading... |
| 2. Things to consider when using GPioses: * Initial powerup status (WPD, WPU, X) * Function of GPIO: I/O/T * IO_MUX function（Any GPIO or Special GPIO） * Driving current * Power domains * Voltage tolerance |
Loading... | |
| 3. Leave GPioses floating if not used. | Loading... | |
| 4. When using a module, note that some GPioses are occupied or the levels of some GPioses are defined. | Loading... | |
| 5. Add the appropriate series matching resistor/ground capacitor according to the specific communication interface, etc. | Loading... | |
| 6. Others | Loading... | |
| Flash / PSRAM | 1. Check if the operating voltage range, capacity, SPI mode, read and write mode, tVSL parameters, etc. of the flash meet the requirements. | Loading... |
| 2. Check if the flash's SPI connection is correct, and whether it's two-line or four-line connection. | Loading... | |
| 3. SPI Flash or HSPI Flash depends on the working mode of the chips. | Loading... | |
| 4. Except CS and CLK pins, the other PSRAM pins can be used as the flash pins as well. Choose the function for those pins via CS signals. | Loading... | |
| 5. Others | Loading... | |
| UART | 1. Add a 500 ohm resistor in series to the U0RXD trace to suppress the 80 MHz harmonics. | Loading... |
| 2. Others | Loading... | |
| Packaging | 1. Check whether the Wi-Fi chip package (pin definition, pin sequence) conforms to the one specified in the datasheet of the chip. | Loading... |
| Others | 1. It is recommended that customers check the other parts of the circuit. Espressif will provide appropriate assistance to customers, if need. | Loading... |
| Examination of PCB Layout | ||
| Types | Examination Items | Results |
| PCB Examination | 1. Check the number of the PCB layers. It is recommended that customers use four-layer PCB design. | Loading... |
| 2. Check whether the PCB design conforms to requirements. The RF traces need to be on the top layer. Use the adjacent GND layer as a reference. | Loading... | |
| 3. Customers are suggested that they examine the PCB DRC themselves. | Loading... | |
| 4. Others | Loading... | |
| Power and Ground | 1. The ESD port of the power input interface should be placed near the port. | Loading... |
| 2. Check whether a 10 μF decoupling capacitor is added to the power supply before the power traces reach the power supply pins. It is recommended that a 0.1 μF capacitor be used with the 10 μF decoupling capacitor. | Loading... | |
| 3. The width of ESP8266EX/ESP8089/ESP8285's trunk power trace should be 15 mil or above. The width of ESP32's trunk power trace should be 20 mil or above. There must be no acute angle on the power trace. Check if the size of the vias on the power trace is appropriate. | Loading... | |
| 4. All the power pins of the chip should be connected as required. The decoupling capacitors should be placed close to the power supply pins. The LC filter circuit added to the PA power supply should be placed near the pin. There should be ground vias near the ground pin of the decoupling capacitor. | Loading... | |
| 5. The Ground PAD at the bottom of the chip should be connected to the ground plane through at least nine ground vias. | Loading... | |
| 6. When using a module, it is recommended that the GND pad at the bottom of the module be soldered to the substrate for better heat dissipation. | Loading... | |
| 7. There should be a divide between analog and digital power, as well as between the analog and the digital ground. The separation of power and ground plane should be reasonable. | Loading... | |
| 8. When using copper for the power plane, check whether the copper width is too limited and produces power supply bottlenecks. Avoid excessively dense ground vias which can affect current-carrying capacity in the power supply copper area. | Loading... | |
| 9. Others | Loading... | |
| RF | 1. The impedance of the RF trace should be 50 ohms. | Loading... |
| 2. Check if there is a sudden change in the width of the RF trace or branches of the trace; whether the traces are routed at an angle of 135°or with circular arcs; and whether there are dense vias stitched around both sides of the RF trace. RF traces should be as short as possible. | Loading... | |
| 3. There should be vias on the RF traces from the chip to the antenna; the antenna needs to be on the same layer as the chip. | Loading... | |
| 4. Check whether the RF's second plane/adjacent planes are complete. For a two-layer design, there should be no routing below the RF trace and a complete plane should be maintained. | Loading... | |
| 5. The components in the π-type matching circuit reserved on the RF trace should be placed in the same direction if possible. Copper burr should be avoided. | Loading... | |
| 6. No high-frequency signal traces should be routed close to the RF trace. The RF antenna should be placed away from high-frequency transmitting devices, such as crystal oscillators, DDR, and some high-frequency clocks (SDIO_CLK, etc.). USB port, USB to UART bridge, UART signal lines (including traces, vias, test points, pins, etc.) must be as far away as possible from the antenna. There should be dense ground vias around the UART signal line. | Loading... | |
| 7. When using PCB onboard antenna (Type-A recommended), there should be clearance below the antenna. The feed points should be correctly connected to the ground. | Loading... | |
| 8. When using a module with an onboard antenna, the module should be placed in the corner of the substrate to avoid the interference of peripheral devices. The onboard antenna should stick out of the PCB board to ensure the best RF performance. | Loading... | |
| 9. Others | Loading... | |
| Clock | 1. Check whether the distance between the crystal and the chip is appropriate. | Loading... |
| 2. There should be no vias in the clock input and output traces, meaning the traces cannot cross layers. Check whether there is a copper around the crystal and dense vias stitched around it for isolation. | Loading... | |
| 3. The external regulating capacitor should be placed on the left and right sides of the crystal. The capacitor should not be connected in series to the chip's clock trace and crystal trace. | Loading... | |
| 4. Do not route any other signal traces around or under the crystal. | Loading... | |
| 5. There should be no sensitive components around the crystal, such as other crystal, power supply, magnetic sensors, etc. | Loading... | |
| 6. Others | Loading... | |
| Reset/Enable | 1. Check if the RC delay network is placed close to the chip pin. | Loading... |
| 2. The trace of the reset pin should not be too long, so as to avoid reboot caused by external interference. | Loading... | |
| 3. Others | Loading... | |
| External Capacitor | 1. External resistors and capacitors of the chip should be placed close to the chip pin and there should be no vias on the traces. The 10 nF capacitor of ESP32 needs to be placed close to the chip pin. | Loading... |
| 2. Others | Loading... | |
| IO Application | 1. The application of GPioses depends on the definition of the communication interface. There is no special requirement in general. At a higher data rate, the GPIO traces should be as short as possible, parallel, with vias stitched around. | Loading... |
| 2. The series resistors/ground capacitors on the GPIO trace should be placed as close as possible to the chip. | Loading... | |
| UART Layout | 1. In order to prevent the UART from interfering with the antenna and crystal, it is recommended that the UART traces be placed as far away as possible. It is good practice to place the external interface of UART at an angle of 180°to the antenna. | Loading... |
| 2. The series resistor on the U0TXD should be placed near the chip, so the U0TXD trace on the top layer should be as short as possible. | Loading... | |
| Others | 1. Customers are suggested to further examine the PCB. Espressif will provide appropriate assistance, when required. | Loading... |
请先根据《客户硬件设计审核项目表》中的建议检查修改。
